Analog-to-digital converter systems can be used to convert continuously varying signals such as analog representations of sound into digital codes for storage and for processing in the digital domain. One popular architecture for analog-to-digital converter systems is an algorithmic analog-to-digital converter. Algorithmic analog-to-digital converters can be implemented using modern CMOS technology using switched capacitor techniques. In these architectures, accurate conversion of an analog signal to a digital representation relies on the assumption that the capacitors in the switched capacitor array all have the same capacitive value. No matter how good the processes used to create the capacitors, this is not an entirely valid assumption. The mismatch in the capacitors effects the resolution of the algorithmic analog-to-digital converter. This capacitor mismatch is typically expressed as a number of bits and with modern CMOS technology the capacitor matching is typically 8-10 bits.
One technique to improve the resolution of an analog-to-digital converter is through the use of digital calibration. In this approach, a calibration cycle is performed to measure an error due to the mismatch of the capacitors in the system. The digitized error quantity is stored in a memory system. Calibration logic can then take the stored error quantity and compute a necessary correction to the output of the analog-to-digital converter.
Although certainly more effective than non-calibrated systems, systems that use this calibration technique have a limited tolerance to capacitor mismatch due to the fact that they use a non-calibrated system to estimate the error voltage. In addition, these systems have typically only been applied to single stage or 1.5 bits per stage converter architectures.
Algorithmic analog-to-digital converter systems that resolve more than a single bit per stage are much more efficient for certain applications and, as such, the inability to use the calibration techniques on these multi-bit architectures is an important weakness in prior systems.